I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC-V is great for embedded because companies can build it into custom chips with specifically the functionality they need, and because of how cheap it is for low-end use cases since there's no license fees.
The only real point of contention I see between the two is that this piece goes on to talk about how it's a selling point that RISC-V can be used for both low-end 10 cent microcontrollers, and high-end multi-core processors running Linux. Personally I don't see the benefit of this since you're going to have to recompile your software anyway, and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
The two authors also have a very different definition of what "high-end" means.
Dmitry is talking about high-end application processors that you might find in a mid-range or better laptop, smartphone or server. Armstrong Subero seems to think that anything larger than a "dirt cheap microcontroller" is high-end.
People shouldn't take this the wrong way, but the VexRISC-V cores in Baochip are not "high-end". They are basically as low-end as you can get while still meeting the modern definition of "application core". And that doesn't matter, because being high-end application SoC is not Baochip's design criteria. These cores are actually pretty decent for Baochip's criteria.
The VexRISC-V are implementing the exact style of "classic-RISC" microarchitecture that RISC-V is optimised for. It's basically the optimal niche for RISC-V, before any of the problems start showing up.
I don't think I've ever seen anyone express the opinion that RISC-V can't easily cover the "dirt cheap microcontroller" to "low-end application processor" range, even stretching up into "mid-range application processor". Just that it's really fighting an uphill battle if it ever wants to compete with high-end application processors (and that it's going to struggle in the low-range/mid-range application market because of that).
To add to what you said, I don't see any big issues with high-end prosessors and licenses.
Anyone who spends $200 million to develop a completely new high-end processor microarchitecture every 3 to 5 years is not going to complain about an ARM license too much. You get freedom with $$.
Softbank and ARM managed to burn a lot of good-will with that bullshit (it is a bad sign when I'm siding with Qualcomm), and all for nothing as they lost that lawsuit. But is generally true that the $$ buys architecture licensees quite a bit of freedom.
Not as much freedom as they would get with something open like RISC-V, as ARM have strict rules around private ISA extensions (like how Apple doesn't publicly document AMX). But that extra control is generally a good thing for the health of the wider ARM ecosystem.
First, im a big fan of what riscV has brought into the world; 0.50 cent processors with radios that can reach a kilometer, 8 cent MCUs that you can put anywhere because they are basically free, 8 dollar Linux computers, and 1 dollar WiFi nodes that can run reasonable applications. And also, the first application capable chip you can actually trust to be free of unpublished capabilities.
RiscV is going to win despite its limitations, simply because they can be worked around freely, and the cost per core is zero. Every major company will be making their own flavor, because it’s the only way they can economically own the product of their work. Not many companies can be Qualcomm or Apple, but when a company invests millions in an architecture, they want it to be an asset on -their- balance sheet. It may not be the best starting point, but it’s the only journey that ends in ownership without starting from scratch.
X86 had dominance for decades not because it’s the best architecture, but because it was the best choice. RiscV doesn’t have to be the best architecture to be the best choice for companies to build on.
Can you list the actual chips you’re referring to and additional sources to follow? I’ve finally started playing with ESP32 and recently getting curious about the smallest possible things out there. Also
Then, there is the CH32v303 https://www.wch-ic.com/products/CH32V303.html, which is the lower end of the chips that support minimal floating point and USB host/client. These ones are a bit more pricey, https://www.lcsc.com/product-detail/C5456849.html at $US1.72 each. The extra price is QFP64 (64 pins, quad flat pack) and more features on the chip, USB, CAN, V4F extension giving one instruction multiply and some floating point operations.
Note that the fact that this chip uses an extension, V4F, for floating point (I think?) is part of the argument of Dmitry's piece on the RISC-V. The chip is pretty low price for a fair bit of power.
Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance.
I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations?
If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanently crippled perf, or find a way around the issues.
--
[0] Making chips is an extremely high tech process with decades of trial and error and proprietary secrets, so this would be the logical explanation to me regardless of architecture. But I'm not hardware guy, so I'd love to hear more about this!
> China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanently crippled perf
Not quite. RISC-V application class processors are a new development. They are starting from behind but they are improving faster than the competition. The SpacemiT K3 is 4 times faster than the K1 for example. The Alibaba C950 will be about Apple M1 level performance. And even faster designs are already in the works.
RISC-V is not “permenantly crippled”. It will catch up and maybe surpass ARM. It is more an economy of scale issue than anything.
Intel and AMD have proven that if you throw enough money at the problem, you can make fast microarchitectures despite a flawed ISA, and in many ways RISC-V is less flawed than x86. The things we are debating here are more along the lines of minor nitpicks.
The main roadblock to the existence of fast RISC-V cores is the entrenchment of large x86 and arm ecosystems.
> The main roadblock to the existence of fast RISC-V cores is the entrenchment of large x86 and arm ecosystems.
I'd disagree with that, their existence and decades of a head start mean they've been much more well invested but that's one of the things we're starting to see change, even if it's because of what would appear to be political motivations. We're starting to see a lot of investment into it in China because it looks like it's a reasonable way for tech sovereignty against the x86 monopoly. They've got licenses to some older (not sure about newer) AMD processor designs, I think around Zen2 architecture, for one of their major manufacturing firms but that won't easily let them move forward since they've got to do a lot of work to keep it up with compatibility and performance for newer ISA additions and such. That's one of the reasons they've been subsiding development of LoongSong64 and RISC-V to the point where for a while the larger LoongSong64 cores were illegal to export to some countries[0].
And then you've got a lot of other companies building faster RISC-V cores, for yes more embedded style designs but not the usual traditional embedded designs either. You've got TensTorrent working on AI work loads with real hardware out there that at least for ML stuff can compete on inference if you can get your software to run on it, and then you've got Bolt doing similar for GPU workloads[1]. While both of those are closer to embedded since you're not going to use them as a desktop, they're still making really fast RISC-V cores that could be theoretically turned into a standard RVA23 core by adding the missing extensions to make it work. That's of course not trivial but the entrenchment of x86 and arm aren't quite as daunting as they might have originally seemed.
It's still not as fast as I'd like, simply because I want to start seeing some RISC-V mini pcs get made that are fine for a daily driver office pc to happen.
You aren't disagreeing with the existence of the roadblock, just how hard it is to overcome.
And yes, there is a bunch of funding being pumped into it. I do have hope that some kind of RISC-V linux workstation will be viable in the next 5 years, without sacrificing too much performance or my wallet. I just wouldn't expect that to translate into making inroads into existing markets where x86 and arm have moats, like android/apple smartphones and more typical desktop/laptop workloads (even on linux).
I wouldn't count the AI/GPU stuff, those are generally pretty simple RISC pipelines with large vector units. Though TensTorrent do actually have a high-performance out-of-order rva23 core [1] that would be able to compete in this space. They are currently selling it as a "core for agentic workloads"
x86 is a horrible architecture, but most of the modern high performance processors are x86. They're only now getting around to making comparatively performant ARM chips.
Not having decently performing risc-v chips right now doesn't mean anything other than nobody spent enough time and money on accomplishing that.
the current highest performance RISC-V systems you can buy off a shelf are equivalent to a raspberry pi 5 so they're not terribly behind. in terms of IPC, currently available RISC-V cores are already basically on par with Zen 3 and Apple M1 from what i understand and Jim Keller believes that RISC-V will be the one that leads the way for raw performance.
SiFive P870 and Tenstorrent Ascalon are pretty much Zen 3. Tenstorrent is supposed to be releasing silicon soon. You can license their cores now. SiFive says customers have the P870 already but I am not sure who those are.
With enough effort, you can make a brick fly. X86 proves this. But if you are designing a new flying device, despite the fact that you could make a brick fly, you probably don’t want to design a brick. Why make it harder on yourself?
Riscv took all this information in, and designed a very, very good brick.
the main problem with RISC-V is also the main selling point: there is no single owner company behind steering development and making sweeping decisions
how will that pan out over the long term is really unclear and the reality is performance is actually catching up quickly
> it sounds like there are fundamental issues that prevent performant implementations?
This has always been true, it is just this is one of those projects that gets some people very emotionally invested so such discussions do not happen in public.
See also Android, rust, webassembly, webgpu and so on.
Well the original article is also about RISC-V isn't a great ISA for embedded either, and how that's supremely disappointing because there's no inherent reason why the designers couldn't have learned from decades of ISA research and made it suck even a little less. OP doesn't even defend the ISA committee (unlike HN, somehow...)
As much as people complain about warts in other ISAs like x86, their design decisions made sense back when they were made (or at least, no one really knew better)
> Personally I don't see the benefit of this since you're going to have to recompile your software anyway
The benefit is a unified toolchain. Make a chip, get the entire software toolchain for free.
In the past if you made your own chip you had to write your own assembler, compiler, debugger, etc. Many manufacturers forked gcc but of course it's still a lot of work and the license isn't great (for them, not the user).
This universal compiler toolchain is massive benefit for both the chip makers and the end user.
Different RISC-V dialects might as well be as different from each other as English is from German. Sure, the cognates, family the resemblance, and common(-ish) alphabet make some things easier, but if you're shipping a manual, you still need to do it both in English and auf Deutsch unless you rely on machine translation.
So it is with the family of mutually incomprehensible ISAs called RISC-V.
Yeah I know this mess in PowerPC. There is IBM Power, there is MPC5xx ISA, there is VLE and and several other dialects. Some processors are doing those some doing others, some needs bit to signal if program runs VLE... just crazy chaos.
The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion.
And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.
> The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion.
I assume this is addressing
> and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
If so, could you point at specific SBCs that beat ARM SBC perf?
Take a look at some of the really new ones, like the Milk-V Jupiter 2 based around the SpaceMIT K3[0]. Single core is still lacking but the multi-core isn't all that far behind a pi5 (350 vs 900 single core and 1700 vs 2100 multicore in a geekbench beta version).
And I will note that the other poster didn't say they beat it, just that there are lots of chips being built. I'd imagine that the cores on the tenstorrent cards would blow all the other arm cores out of the water if you could run the benchmarks on them directly, given the much higher core speeds and memory bandwidth etc.
The multicore is only close because the RISC-V one has twice as many cores and uses twice as much power. That would suggest the RISC-V cores are getting around pi3 levels of performance which is a decade old and losing badly as perf/W.
* Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIMD registers to the destination. There are however some instructions where LMUL=2 only needs to write to one registers, those are narrowing instructions (e.g. 64-bit to 32-bit truncation) and comparisons (which write to a LMUL=1 register with packed bits). When those SIMD instructions have to .vx form, which means one argument comes from a GPR, they now only need to write one SIMD register and need to read two SIMD registers. This matches what regular SIMD instructions need and because the silicon for the execution is much cheaper than register file ports, Ascalon can exexute these instructions in a single operation. So you can compare twice as many SIMD elements against a scalar, then you can against another SIMD register.
* Ventana (now under Qualcomm) talked a tiny bit about their fetch-block-optimizer and something that sounded like a L1i-trace cache. The fetch-block-optimizer would go to certain hot L1i entries and "optimize" them, with agressive instruction fusion including fusion of non-adjacent instructions.
* NextSilicon: Idk any details yet, but they said they handled RVC without increasing latency and that they've found a good solution for implement RVV and especially LMUL, which is a challange in out-of-order designs.
* OpenXiangShan: The fastes open-source CPU, is working on doing 2-ahead instruction fetch (the thing Zen5 added).
Now that being said, Ventana was bought by Qualcomm, we know the RISC-V team is still alive, but who knows if we'll ever see anything from that outside of Qualcomm?
The Tenstorrent Ascalon devboard is way behind schedule and on 12nm TSMC instead of a 4nm node the processor was designed for and is now supposed to clock at 1.38GHz. Though I think the delay has more to do with TT management problems then with the actual design.
While the scalar part of OpenXiangShan looks really good, the RVV imolementation is currently basically unusable. They want to have fix for the problems until the end of the year, but we'll have to see.
I basically spend way to much time with RISC-V related things.
But the easiest way to get more info about RISC-V developmemts is by watching the youtube uploads of the RISC-V summit talks.
Every SemiCon usually has a RiscV forum. Obviously there are also RiscV events. Wesemibay usually has several RiscV processors and GPU's from new vendors and you can then go and check what features they support. But basically as with everything else you have to show up and talk to people, or just look at the summaries afterwards.
Hard to know at this point. In the past ARM sued people for daring to think about implementing ARM compatible computers. (Even university research projects.)
Of course, in the more distant past, AMD and Intel sued each other a lot. But there have been a dozen or so x86 market entrants. I think the competition has just been brutal.
So, with either one, you could, of course, do a clean-sheet design and hope you don't get sued.
Since ARM has historically only sold IP, they are incredibly jealous of their monopoly for that ISA. Of course, the flip side of it is that if you have enough money, and you beg and grovel enough, you can probably do what you want with their code.
Except, of course, when you can't. Or rather, maybe you can, but they will try really hard to stop you.
For example, Qualcomm, an architecture licensee who had purchased the rights to basically make whatever the fuck ARM they wanted, purchased a startup named Nuvia that also had an architecture license, and started using Nuvia's designs.
ARM sued, just because. They were shut down in court, but the message is clear. They are very aggressive.
Seriously, who needs that shit? Semiconductor market windows are tight enough as it is, and ARM has always acted like "Nice chip you've got there, buddy; shame if you haven't dotted your i's anc crossed your t's on the licensing."
At least with Intel or AMD, you're probably only looking at patent lawsuits, and you could probably do a decent job on a low end machine with techniques that were known 20 years ago.
You could do the same with ARM, of course, but they will sue you just because, to see if they can make you run out of money.
I don't really understand the author's conclusions about cost and shipping, and how RISC-V is cheaper and more accessible to people outside the US and Europe. He first talks about how getting $1 worth of chips can cost $60-$200 in shipping for him due to his location... but then by the end claims that RISC-V gives him "an architecture that arrives in my country at ten cents a part".
I don't get how both things can be true. The cost to ship something to Trinidad and Tobago has nothing to do with whether it's ARM or RISC-V; shipping the same weight of either kind of chips should cost exactly the same amount. Yes, maybe the chip cost itself of a particular ARM-based model is $0.15 while the equivalent RISC-V chip costs $0.10, but if the issue (for him and other people who live outside US/Europe) is that shipping costs are orders of magnitude more expensive than the thing being shipped, that chip-cost difference becomes irrelevant.
I think he does make a great point about how fragmentation does give you better optionality: ARM is sort of like cable TV where you have a small number of product categories that each bundle a particular set of features, whereas with RISC-V you design something bespoke that does exactly what you need and nothing more. But again, this isn't going to affect shipping costs.
He's saying that shipping from the big western parts suppliers (Digikey, Mouser, Segger) costs a lot of money. When ordering from AliExpress or Crowd Supply he just gets the cheap postal rates which from China are free. It is very likely a good chunk of the overhead from western part suppliers has to do with export controls and risk aversion.
Aliexpress doesn't do any ID verification hassle. This is all an argument more about distribution and shipping. RISK-V is going to win because getting the parts is insanely cheap and without overhead.
The "fix" is probably Digikey, Mouser, and Segger need to just let buyers check a box where they assume all liability and parts are just thrown in the mail and forgot about - something aliexpress is great at doing.
Is the only source for ARM chips the big Western parts suppliers? If not, and you can get them from AliExpress or Crowd Supply, then, again, there's no difference in shipping between ARM and RISC-V chips.
A quick search for "arm chip" on AliExpress shows lots of results, so I don't think your argument refutes anything I said.
The other thing he doesn't mention is time, I live in AoNZ and we do get free shipping from Digikey if we order over a minimum (~$60US) - but the big deal is time - you have to order everything you need ahead of time and get it all to arrive - miss one thing and you're stuck with a PCB and a box of bits and are sitting on your hands for a couple of weeks - you have to be incredibly organised - it's why I have a cabinet of SMD reels most of which I'll never use (reels of common components are ~$2 while visiting Shenzhen a couple of hundred $$ saves you a bunch of pain)
Living in the US and having free overnight delivery is 1st world luxury
Also note: LCSC sells PY32 Arm Cortex-M0 (PY32C642-C) for half the price (0.06$) of the cheapest CH32 [CH32V005D6U6] (0.11$). Given it has half the RAM, but price matching yields a better chip for less or the same money.
STMicroelectronics also launched the STM32C0 series that is still quite cheap @ ~0.35$/piece.
However, the prices on aliexpress all mishmash so giving a correct quote is impossible as the same chip is sold at wildly different prices by different sellers.
I don't know if we should jump immediately to that conclusion. The article has plenty of tiny typographical/grammatical errors suggesting it was human written, or at the very least a human was significantly involved in the loop.
I hadn't thought about it, but yeah, that does sound like Claude.
But it doesn't change the question; I still expect authors to be responsible for the meaning of what they post, regardless of whether they fully wrote it themselves or not. Yes, I know, silly me.
In addition to what you wrote... what does China use? One could argue that the factories there have very low cost of shipping + economies of scale - they order thousands of units, if not tens of thousands.
Then probably RISC-V being "open" license is the key to its success, even if the architecture itself is weird.
I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64.
This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86 computers of the era.
However, people were buying x86 computers at a far higher rate, giving Intel (and AMD) the money needed to invest in better chip designs and better fabs. Linux was, at the same time, gaining traction and, around the time the dot-com bubble popped and there were no longer companies with the money needed to get Sun SPARC workstations (or what not) at $50,000 or more a pop to start up a web business, x86 computers running Linux had nearly the same performance at a much lower price. Once the Itanium sank and x86_64 was mainstream, x86_64 was the ISA of choice for performance workstations and servers, and the RISC ISAs that survived were now mainly used in the embedded space. Indeed, ARM was never a high performance RISC processor, and it was the one that took over the embedded space while PA-RISC, Alpha, and SPARC died.
The ISA for what were cheap computers become the highest performance ISA around.
It has been only in the 2020s that RISC processors have gotten x86_64 levels of performance, notably in the the Apple M series of processors. So now ARM, an ISA which was geared for cheap embedded devices, has become a high performance processor, in line with x86.
Right now, RISC-V is mainly being used in cheap embedded components. Considering that x86 and ARM also were made for cheap computing, until becoming the dominant high end processor, history tells us that the cheapest ISA is the one which will become the highest performance one.
RISC-V currently has about the same performance as a high end Raspberry Pi. I predict it will have medium-level PC performance by the end of the 2020s.
It's fascinating to me what you're describing. That ISA prevalence basically comes down to the anarchy of the market, and theoretical differences in the actual design don't really factor in. Is this true? Can we analyse the reasons we expect RISC-V to have better performance, and possibly even extrapolate that to a theoretically even better ISA and skip over RISC-V entirely?
Getting RISC-V to have better performance is a matter of in-chip optimizations (caches, pipelines, etc.) and high quality performance oriented fabs. The dominance of x86 after the dot-com bubble popped shows that one can get incredible performance even from an ISA which is a hack on top of a hack on top of another hack. [1]
In terms of a “theoretically even better ISA”, if anyone has any proposals, I would love to see links to them. In particular, the article “RISC-V: They Should Have Known Better” does not propose an ISA (except mentioning that the author feels AArch64 is much better), so I find its criticisms dubious.
[1] I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers, but 16 registers at least is quite a bit better than the 4-8 registers the 386 had.
But is there any article / papers / field of study that explores the theoretical maximum of various architectures, given infinite resources? Do they begin to converge, such that a highly optimized Arm looks similar to a highly optimized RISC-V core? If we are near / past the point of diminishing returns for x86, how mathematically rigorous is our proof of that?
> [1] I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers, but 16 registers at least is quite a bit better than the 4-8 registers the 386 had.
Is "registers" still a real thing or its just an illusion at this point? I am pretty sure there are "virtual" registers or micro instructions (something like that, I forgot the terminology)
> From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings
Yet earlier:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
Seems to me that the difference between a 10c chip and a $1 chip are a rounding error when the shipping cost dominates so much?
> I can pick up H417s on the official WCH store on Aliexpress with free shipping and no verification hullabalu.
I think the point is that anyone can make these chips, so there are Chinese sellers who just throw them in a padded envelope and send them out without bothering with all the stuff "serious" vendors do. And because they're cheap enough, if doesn't matter if some get lost in the mail.
Sure, but a quick search of AliExpress shows that you can get lots of ARM chips from them too, and I assume those are without any "verification hullabalu" as well, no?
In the article, he addresses the issue of clones vs 1st party RISC chips on AliExpress. As a mere dabbler, I have been bit by undisclosed errata on an STM-compatible/bootleg/clone/counterfeit Arm chip while using the official STM SDK.
Maybe. There's less wiggle room though. You can't make a clone of a WCH, ESP32, GD32V, or RP2040 at a low enough price point to really profit from the gap.
If Quintauris successfully makes a RISC-V range for automotive use, there'd probably be margin to clone those and sell at a profit, but skirting automotive certification regulations is a high-risk game that (hopefully!) doesn't have many buyers.
If they make an IoT line, again, there might be margin in it, but you'd be trying to fit in between buyers willing and able to engage with Chinese sellers but for some reason unwilling or unable to engage with existing Chinese sellers of existing IoT RISC-V parts. Quintauris is a very, very long way away from being a "household name" along the lines of STM32 or FTDI.
> Sure, but that problem should exist for both ARM and RISC-V.
I don't know why you'd take that as a given when marquee RISC-V microcontrollers are almost universally low-cost, but Arm has pricier marquee parts, thus a bigger opportunity for undercutting the market leader on price with a cloned product.
I’d really like an explanation here if the author is reading. And how does shipping cost scale with quantity? Can you get that to be small per unit on big orders?
Hi there, shipping has a floor and then it scales, but it scales far slower than the order does.... so if you buy like one resistor from DigiKey or Mouser, that starts around $60, a hundred resistors costs about the same if you add chips and weight and it climbs from there, but $60 is the floor no matter how small the order....
So per unit shipping collapses with quantity, which is why the part price matters more here, not less. The fixed cost forces you to buy deep, and only the cheap part lets you buy deep. At a dollar a part, 1000 units is a $1060 order nobody here is placing... at ten cents it is $160, and then there are 1000 parts sitting in Trinidad that nobody else has to pay $60 to reach, so you can have enough for a small product run..keep in mind we also currently have US dollar shortage, so you only get allocated a certain amount of US per quarter....
I should also have been explicit that those figures are the Western channels like DigiKey, Mouser, courier from LCSC. WCH officially sells direct on AliExpress with free shipping, which runs on postal consolidation rates that do not price by how remote you are. But that channel is a game of chance. Sometimes things just never come, there is no ARM equivalent either. I cannot buy an STM32 from ST with free shipping to Trinidad, and I cannot trust the aftermarket parts because some of them are fakes, and some vendors do not have this country in their shipping list at all....
The part I care about most is that at ten cents I can hand a student a part they are allowed to destroy. Learning embedded means killing chips, and at a dollar a part a teacher flinches, cause 1 US dollar is about 7 dollars here, and starts supervising instead of letting people find out. And the same goes for me, at ten cents I can experiment and still ship with the part I experimented on....
> at ten cents I can hand a student a part they are allowed to destroy. [...] at a dollar a part a teacher flinches
Ah, I think that explains my confusion (in a different top-level comment[0]).
I read the wording in your article as you getting shipped "a dollar worth of chips" or "a dollar of chips", which to me sounded like you were talking about ordering multiple chips. So I assumed that the per-chip cost for ARM and RISC-V were close enough not to matter too much, and the shipping cost easily dominated.
But now I see it says "one dollar chips" (either I read it wrong initially, or you've updated it since I read it), which makes sense. $1 vs. $0.10 is a big difference at even smallish quantities. (My assumption was that the chip cost difference was more like 1.5x, not 10x.) And while the shipping costs are huge enough to dominate regardless, being able to order 10 chips vs. 100 chips for the same price (and presumably roughly the same shipping cost, even if it is high), is a big deal. The "allowed to destroy" bit is very real.
I thought your argument was about shipping costs, since that's what you focused on so much in the article, but the real issue is still the cost of the chips themselves. The ridiculous shipping cost you have to pay is certainly a factor, but I think a teacher in China would still flinch at giving a student an easily-destroyable $1 part, vs. a $0.10 part, even if their shipping costs are basically nothing.
I love the article, it's a breath of fresh air compared to the usual bay area centric takes. However there's just one issue:
> The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh
It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile delivery costs are fairly low there too.
Is this comment on shipping costs from Asia to Nigeria/Bangladesh based on your experience? If there is a less expensive way then share the approach to help others :)
It could be bureocratic barriers. For example, Turkey recently changed importing laws so that anything(even stuff sent to you for free) from outside the country is subject to tariffs & import costs. Importing a cheap component worth 1$ costs like 300$.
i don't know how trustworthy rateships.com is, but according to them shipping costs to nigeria and trinidad are similar. and as for the last mile, the cost probably goes up because local shipping is rather unsafe (higher rate of theft of packages).
I am in Asia, this means nothing, it's the largest continent on earth. I don't pay as much for shipping as the author does, but his struggles are nevertheless relatable: most sellers refuse to ship here, most of those who do want dozens and dozens of dollars for it, and some (few, usually Chinese) sellers save the situation from being completely hopeless.
In my experience, people in the United States often (incorrectly) short hand East Asia as Asia just like the people in the city of New York will often (correctly) short hand New York City as New York.
> In my experience, people in the United States often (incorrectly) short hand East Asia as Asia just like the people in the city of New York will often (correctly) short hand New York City as New York.
In my experience, the only demographic who complains about “Asia = east Asia” are people from South Asia, aka Indians/desis
Ironically (for my generation in the UK at least) "Asian" meant "South Asian" and for a long time we didn't have a useful shorthand for "all parts of Asia"
1. "Asia" and "Asian" are different words, which mean different things.
2. There is a dialectal difference specific to "Asian" between England, where Pakistani immigrants are prominent, and the United States, where they aren't.
Asian to Brits definitely means South Asian(probably includes West Asians but I'm not sure about that). They were already bitching about this 30 years ago when the net was standardizing on American English where Asian means East Asian.
The term for East Asian was Oriental which is now considered racist/passé for some obscure reason.
When the term started out, There was nothing called United States (As a country or its current culture/s). And I am not sure if this happens outside the US anyway.
In the context of microcontrollers and electronics, the likeliest intended meaning was shipping from China, South Korea, Taiwan and perhaps Japan, because that’s where the bulk of the fabs are.
> It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh
So don't even try to find how expensive is bring these to Brazil. Even the $5 orders from JLCPCB become infeasible for hobbyists here due to all the roadblocks.
> it's a breath of fresh air compared to the usual bay area centric takes...
HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with SWE culture in DACH and CEE.
Presumed RISC-V hate is a perfect example of that - the UCs and CSUs have been using RISC-V in their curriculum since the 2010s becuase Patterson is faculty at Cal and most CompArch courses in both systems have been using RISC-V as a result because 61a/b/c are often used as the benchmark curricula wise. An entire generation of Californian computer engineers have been RISC-V fluent as a result.
The hivemind assumption that HN's user base is "venture capital", "tech bro", "founders", and "Silicon Valley" is around 5 years out of date.
Anecdotally, the vast majority of younger (below 30) founders, engineers, VCs, and builders in the Bay have either not heard of HN or quit it within weeks due to toxicity.
>HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with DACH.
I honestly do not get this at all. HN remains very US-centric to me, and especially centric to the mindshare of the Bay Area's IRL conversations, and apart from some takes on tech rights, does not really remind me of my experience in DACH.
As someone from the DACH region I very much agree with this. I don't see a shift from typical US opinions to opinions often held in the DACH region. Not at all.
> I honestly do not get this at all. HN remains very US-centric to me, and apart from some takes on tech rights, does not really remind me of my experience in DACH.
The majority of HN's usership, posting, and comment activity occurs during peak EU work hours (3am-9am), stylistic patterns that are common for German-, French, and Polish-native speakers are increasingly prominent (eg. periods and spaces instead of commas in numbers, spacing between quotation marks and words, failing to use context clues to infer timezone), and the fact that IRL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase.
HN "Who wants to get hired" threads are a good example of that as well.
I'd recommend deep diving in the HN scrape dataset on HuggingFace [0]. The site has diverged heavily compared to 2018 or 2012.
> How would you say the "IRL conversation topics in the Bay Area tech scene" diverge from HN
For starters, most Bay Area residents are not active on HN on a sunny Sunday afternoon during peak brunch time, a Giants v Rockies game, a social race in the Marina, during the weekend right before college move-in begins for a number of UCs, and the first weekend after the K-12 school year started.
Secondly, the technical conversations on this HN are somewhat divorced from those which are common now. Firstly, no one cares about system cards or micro-level model changes and performance anymore - the name of the game now is eval, harness development, RL/reward engineering, and model-agnostic development.
Thirdly, the vibe change around layoffs the job market is completely different. While there have been plenty of layoffs (and friends and acquaintances of mine have been impacted), most have been able to land jobs within weeks with a similar base/bonus/equity structure.
Furthermore, the Ivy-versus-nonIvy division and rhetoric is nonexistent in the Bay. Everyone here knows a UCLA grad has the exact same opportunties right out of college as a Stanford grad. Most high value careers like startups, PE/VC, big tech, etc recruit from a mix of 20-30 public and private schools that I have listed multiple times on here. And to add to that - "MBAs" as a moniker is nonexistent as most of us who are in decisonmaking roles here in VC, Corporate leadership, and mid-level management are engineers who never did MBAs or any kind of grad school (except our Chinese/Indian peers because of the F1 OPT).
Additonally, most people are levelheaded about AI - they don't deride it as useless but they also don't think it's going to destroy all jobs. On HN you get very black-and-white and highly polarized thinking that AI is only going to lead to X or Y.
And finally, I notice a degree of European anti-Americanism and American anti-Europeanism that is nonexistent in the real world. I have co-hosted events with EU consulates, helped direct European startups to get American funding, and vice versa, and had pretty personal and unfiltered conversations over drinks with pretty high level Europeans and Americans, and the kind of acrimony you see on here is nonexistent IRL.
Not a single mention of pickleball, hyrox, Kdramas, Yemeni coffee, women's basketball, and other stuff currently in the zeitgeist in the Bay is very telling.
This is a good example of someone who is out of the loop.
Luma was always a public events app optimized for discovery. Partiful on the other hand was meant to be a a replacement for FB private events when hosting a house party or private gathering. Basically, Luma was always designed for M-F and Partiful was always meant for Sat/Sun.
While I appreciated your source
1.) I doubt 99% of Europeans work during 3am - 9am
2.) At least there can be other reasons:
2a.) EU times and African times are basically the same and Africa has a huge population.
2b.) India is closer timewise to EU/African time zones
2c.) What are about posts afterworks?
" RL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase. "
Any proof?
I disagree with some points in "RISC-V They Should Have Known Better".
For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM is better because it has a "store multiple registers" instruction. It wouldn't help because storing multiple registers still requires multiple bus cycles, and microcontroller probably has a 32-bit bus and no cache, so saving N registers requires N memory cycles - no matter, is it done with a single instruction (ARM), or with multiple (RISC-V). And implementing this ARM instruction makes the core more complicated with little benefit.
As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment.
The real weak points of RISC-V are:
- no trap on integer overflow and invalid FP results . Overflows cause vulnerabilities
- no optimizations for fast context switch, which is required for dumping legacy unsafe monolithic kernels, especially in age of AI actively searching for vulns
> He derives the case for the chip and then spends the rest of the article annoyed that the chip exists. This is almost satirical.
His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?
Because the people driving the RISC-V ISA all care about delivering IP and not chips and, as such, only care about the high end portion of the market.
The problem is that RISC-V is never going to win at the high end. RISC-V will never have as much money driving it forward as x86 and ARM. As such, the blocks and integration will always lag.
The portion of the market which RISC-V could dominate is the low-end (you know ... the same way ARM climbed up the ladder?) and nobody in charge of RISC-V cares because you have to actually ... SHIP FREAKIN' CHIPS ... and that's, you know, so icky.
And this is the disconnect. Low-end embedded has a bunch of needs and the RISC-V architecture completely whiffs on many of them and has active misfeatures on others while having very little that is actively good in that space.
And many of us are angry about this. It didn't have to be this way.
Maybe. I'm not sure if the original author's intent was to say how risc-v could be better or to say it is bad and people should use other (proprietary) ISAs instead.
Before this, the author has never recommended others stay away from RISC-V, just stated their own distaste for it and a personal preference to use any other ISA if given a choice.
I am sorry if my point was not clear enough. I don’t advise anybody to stay away from it. In many ways it is good enough.
I just think that if you were designing something from scratch, you could actually learn from past lessons, rather than publishing a document saying you learned, and then demonstrating conclusively that you didn’t.
At least for me, I agree with both of the things you said. RISCV is a significant improvement on a lot of of the status quo in situations where it is currently getting design wins. But it also could’ve been a lot better in simple ways that should have been thought of.
Yeah the complaints in the original article are valid, but it's like complaints about Android or iOS. There are plenty of valid complaints against either, but neither is strictly better than the other.
I lost the thread of his argument when he brought up the shipping expense:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
then follows with:
> the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings.
When shipping is so expensive, doesn't the difference between $1 and $.10 unit cost become less relevant?
Though it feels a bit strange that "I have exceeded the allowed number of requests. (500 times)" when I first clicked the article and I'm pretty sure I don't share the ip of my self-hosted VPN with anyone.
I mean that is not even 10 page view per second. We are not living in 2006. Actually even in 2006 Apache with static page would have been able to handle that on a small VPS. And that is excluding CDN.
My perspective using Nix is that it's hardly worth standardizing ISAs. Recompiling software is easy and we should have a Cambrian explosion of different designs.
This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.
I disagree, compiler optimization and software ecosystem in general already take a really really really long time to build, and I think it'll take longer without a standardized low-level binary interface i.e. ISA to enable rapid distribution.
And the approach you mentioned here:
> a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA
I think this is basically WebAssembly and PTX, and one may argue, Java bytecode. Yet look at how much efforts and time it took for WASM runtimes and JVMs to actually produce performant machine code (the "last bit per ISA" you mentioned) for just a couple of architectures! (e.g. X86 and ARM). And I wouldn't surprised if NVIDIA pour even more money on building optimization pipeline from PTX to each of their different uArchs.
What exactly does a bespoke ISA buy you? What will justify hundreds of engineers writing a new good one & working through the compiler support?
I bet it would be pretty easy for a user to interoperate between 67 different drafts of the HTTP spec once they were all written, validated, and library implementations coded. But what would that Cambrian explosion of API revs actually get you?
An explosion of ISAs means the available talent for writing optimizing compilers will be stretched much more thinly. Unpopular ISAs will have slow, buggy codegen, and the popular ones will suffer somewhat, too.
I don't think the Author disagree with what the original article wrote. If anything everything he said seems to reassert what the original article intended to state.
And while things has died down a lot in the past few years, there is a reason why I wrote the line.
"You do not criticise The Rusted Holy Grail and the Riscy Silver Bullet."
>He derives the case for the chip and then spends the rest of the article annoyed that the chip exists.
>This is almost satirical.
That's all that needs to be said.
It's like comparing Unity and Godot. Unity is better in every single way but one, you have to license it from a very poorly ran company.
You don't "own" your games, they ship with black box spyware. The pricing for using it can change from day to day.
I swear the Unity C level employs a Magic 8 Ball and consults it for key management decisions.
If you need to edit the Unity Engine source code your looking at a secret additional licensing fee which is certainly unaffordable for hobbyist and most indies.
Vs Godot which is completely free under the MIT license.
Everything about the above can be said for ARM as well.
RISC-V is free for everyone to play with. If you think it sucks you can always fork it and jerryrig it to work on existing hardware.
If you have money you can even get custom hardware for your forked RISC-V.
I very much enjoyed reading this article, I'm optimistic in seeing what OPs students come up with. This is life changing technology that's essentially available to all.
I'm not a professional game maker. But having used unity in anger in the past I found Godot a breath of fresh air. What unity really wins with is the unity asset store.
Which may actually be a good analogy.
One thing I've seen rarely discussed is existing expertise/experiance, existing varification/tooling and existing quality reference implementations.
Arm wins in all of the above over RISC-V currently, if you have the money to license from/work with Arm.
I totally agree. Trinidad & Tobago isn't a poor country. It is a petro state (oil and gas) in the Caribbean. GDP per capita is 20K USD. That is middle income.
"Now price the same journey on the other side, forget x86-64 and that duopoly, patent minefield, with multi-thousand dollar debug probes; we'll take a look at ARM."
The 386 and 486 patent should have expired more than 20 years ago. No one tried to open source it. https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/0... There were many companies that had clones in the early 90s, and I wonder whether any of them still have the rights to manufacture them.
" That is a better reason than elegance. and I want to tell Mr Grinberg, that the word priviledge he tosses around in his article also extends beyond the ISA depending on where you are in the world."
Grinberg is an emigre from Ukraine, which isn't the most privileged place in the world. In fact his research articles go deeper than the average software developer in Silicon Valley.
There are 386 and 486 open source reimplementations in Verilog (see z386 and z486). As far as I know, existing commercial 386/486 chips still manufactured (yes they exist!) are descendants of Cyrix work, not Intel or AMD. Consequently, VIA may be contractually holding those back rather than Intel/AMD doing anything there.
Thanks for that information! I have been interested in getting x86 produced in smaller nanometer (e.g. <32nm). My project: https://ei2030.github.io/FemtoTX/#about
"Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere."
What's interesting is that a startup with limited funds would most likely seek a 32-bit x86 license if a) they don't need more than 4GB of RAM, and b), if they don't want to pay AMD for the 64 bit license add-on. :)
I'll also point out that we've always had better starting points for open source high performance cores. SPARC and POWER both have open ISAs and open-source cores with useful performance. The UltraSPARC T1 and T2 processors were open sourced under the OpenSPARC project. POWER has the OpenPOWER project governing the Power ISA, and IBM itself created Microwatt, Chiselwatt, and the A2I/A2O cores as open source that people can build their own PowerPC systems from.
OpenFirmware came out of OpenSPARC and is also used by POWER too. Parts of it are used in ARM and RISC-V today (mostly DeviceTree, though arguably quite badly).
Nobody actually wants to make good cores for cheap. Nobody wants to make compatible systems unless forced to. That's why ARM and RISC-V are fragmented messes.
True, and the only reason I'm partial to x86 and even some older ARMv cores is that there is a huge existing software ecosystem already available, reducing the need to develop new bootloaders and ports, as coding hours aren't free. CISC cores are treated as if they are a dirty word, but are more versatile for covering various applications.
PowerPC at least still has a living ecosystem, even from the bootloader level. GRUB can boot from an OpenFirmware system. There's also yaboot if you hate yourself. ;)
I would personally love to see more Power Systems based projects. Everything is out there, just someone has to want to do something with it.
Fedora Linux even fully supports POWER8+ little-endian systems, and Fedora KDE offers a live ISO you can install on something like a Talos Workstation.
Cyrix famously had to skirt IP laws by using TI and IBM foundries because those two companies had full Intel 3rd party licenses. Cyrix was sued and paid big bucks settlement just to be able to use Intels patent 338 (long expired). Later cross licensing had little to do with Cyrix, and more with National owning crapload of patents they could use to retaliate against Intel - that 1998 deal https://www.intel.com/pressroom/archive/releases/1998/CN0203... resulted in full cross licensing allowing National build straight 1:1 copies of Intel chips if they desired.
When VIA bought Cyrix from National they didnt inherit ANY of those licenses. VIA was sued just as original Cyrix and National did, and once again had to pay big bucks to settle despite just aquiring Centaur with a bunch of patents and Intel license https://www.pinsentmasons.com/out-law/news/intel-and-via-set...
High shipping costs are the reason why many countries in the Caribbean and Latin America usually have freight forwarders They locally market themselves as package lockers, po boxes or online shopping companies. It turns out the expensive shipping cost doesn't scale linearly with package size or weight. The expensive shipping cost is a base price, and only rises slowly with package weight and size.
So, these freight forwarders rent a warehouse in the US, an LLC in the US for paying rent, and give away the address of the warehouse to their customers locally. Customers use the address when shopping online and their packages are dropped off at the warehouse. Then they employ people in the US to collect customer packages in the US into large bags, which are then shipped to the destination country via DHL.
DHL does charge the exorbitant shipping to third world country fees of 35 to 60 to 200 dollars that people here complain about. These fees are the base price for shipping, no matter how small or light the package is.
Then, to recover the fees, packages are handed over to customers at a minimum of 2.50 dollars per pound, per package.
For the business to work, income from these packages has to exceed the shipping cost. In Panama, you can probably fit 100 average packages into a 25 pound bag. That bag costs like 75 dollars to ship from the US to Panama. Then you make 250 dollars when people collect the packages. Local customers trade speed for cost, trading the 35 dollar base shipping price for 2.50 dollars and an extra week of lead time to wait for collection to complete in the US. They also don't have to go to the airport to pick up their packages since the business is ideally close to their house.
Businesses like Temu ship directly from china via companies such as PRS logistics and J&T express so their shipping costs to third world countries are lower and can thus bypass freight forwarders entirely so freight forwarders only remain for items sold within the US, where shipping to third world countries has a base price of at least 35 dollars, and whenever shipping to your country costs that much as a base price, even if it ships from China, or when a business only offers shipping to or within the US.
Sometimes, temu is more expensive than a Freight forwarder, but the user is freed from having to handle any logistics like using a particular address and choosing and registering with a package locker and travelling to pick up packages there and the shipping price remains under 10 dollars. However you still have to use a Freight forwarder for items over 120 dollars such as laptops and some car parts because temu doesn't carry those. Freight forwarding is also done in the exact way described above in China instead of the US because websites like taobao rarely offer overseas shipping. Again employing people in china and renting warehouses near airports there. Freight forwarders also offer marine freight instead of the default air freight.
Of course, renting a warehouse and employing people in the US is expensive by local standards. Worker pay alone is around 1600 dollars vs 600 locally. So, there are only a few freight forwarders which often offer b2b, and then package lockers use their sevices. To the end customer there is no distinction between a package locker and freight forwarder. Some freight forwarders also offer B2C package locker services, others are B2B only.
For example nelcon cargo, Uno express, airbox, mail boxes etc are vertically integrated because they are both B2B and B2C, cft cargo is B2B only. most package lockers do not do freight forwarding themselves and use a B2B service for freight forwarding, the package locker only offers proximity and thus convenience to neighborhood customers. Air freight via Miami international airport is the default, and most freight forwarder warehouses are located near this airport. In China, the bottleneck is not price, but speaking Chinese, so it is often run by locals of Chinese descent and is more niche than shipping from the US. This also means that taobao has a lower shipping volume and thus a smaller local market.
Buyee and Zen market, so called proxy services, are very similar to freight forwarders but the service is allowing foreigners overseas to purchase in Japan because most japanese companies do not offer overseas shipping. And there are a few freight forwarders in china as well.
This blog post is very defensive and argumentative, which I guess is fair considering Dmitry's post is similarly inflammatory, but most of it was really not convincing:
> Simply put, the things a high-end CPU needs are diametrically opposed to the things a small cost-saving microcontroller core needs.
> The conclusion he draws is that no single ISA can serve both ends, and that RISC-V fans are fooling themselves, in theory the premise is true. The conclusion does not follow, and I can show you why from three parts sitting on my desk as we speak.
> CH32V003. This is the cheap "RV32EC" with sixteen registers, no multiplier, no divider, machine mode only,
> CH32H417. A dual core MCU that is unmatched in performance to price point and is at the higher end of the MCU line
> Baochip. A VexRISC-V with an MMU built around a stack thats open from silicon to os Baochip-1x: A Mostly-Open, 22nm SoC for High Assurance Applications
Uh, which one of these is a datacenter server cpu? Or a workstation cpu? Or at least a developer laptop cpu? How about a Raspberry Pi 4 level SBC (supporting latest ubuntu and fedora releases, driving a display that runs a browser and plays video ...)
There's a lot of angry indignation but it seems obvious that Dmitry is quite right about this.
But I found this is where this blog post starts making a lot of sense:
> Has anyone tried adding an MMU to a Cortex-M? The physical tradeoffs are real, the difference is that with RISC-V, the ISA owner does not decide for you where that boundary must be drawn. If you want virtual memory on ARM you license a Cortex-A instead, which is a different core family, a different profile, a different negotiation, and a different royalty.
> Compare what happened with Baochip. The RISC-V privileged specification defines supervisor mode and Sv32 paging as optional things an implementation may provide. VexRISC-V is an open core, somebody added an MMU to it. bunnie built a chip around it and runs a microkernel with real process isolation on it
Yeah, that is a good point. We're still in the low-end specialty realm, but that is real interesting advantage for RISC-V, a good reason for it to exist.
As for shipping to Trinidad and Tobago ... this post is trying too hard to turn this into moral issue, but it seems a bit random (OrangePi cost $30 and shipped free? you can also get arm-based and stuff from the same places), and the vast majority of people don't live on semi-remote islands, it doesn't make sense to consider this kind of accessibility above all else, and it's strange to blame Dmitry for not thinking of you here.
the author just focused on his personal experiences regarding RISC-V and what he's been able to see himself as an embedded developer. there's already RISC-V SBCs that are on par with the Raspberry Pi 5 and in terms of IPC the best RISC-V cores are only lagging 5 years or less behind the best x86 and ARM cores.
no, i'm talking about the core designs, not finished CPUs you could buy. using a leading-edge node is prohibitively expensive so nearly everything RISC-V i've seen has been using around 22nm to 12nm nodes. if you had an example of any of those cores in a finished product on a similar node they should be competitive, and in the meantime once people can get their hands on them you could test them against each other at low clock speeds to see how they compare.
I read the "They Should Have Known Better" article and forgot it. I've seen this before. I know it's hot air and does not matter, and I can't afford to worry about things that don't matter.
When I say I've seen this before, I'm talking about ancient history: controversies so old and so laughable that they've been forgotten. When, for example, AMD handed the world AMD64/X86_64, the same things were said: fragmentation, legacy+flawed ISA, etc. That has not aged well, and "They Should Have Known Better" won't either.
The "fragmentation" argument has no merit. The jumble of extension names and profiles in RISC-V are, in fact, direct evidence that RISC-V is succeeding: it's the RISC-V ecosystem aggressively, collaboratively and successfully tackling pain points and solving them. This is what RISC-V is supposed to be doing, and it's doing it, and empires are being built on it.
Take this part: "The existence of CLIC and various proprietary 'fast IRQ' / auto-stacking extensions is an additional indictment."
CLIC is miraculous. It's an advanced embedded interrupt controller, and it's wonderful: it brings the equivalent of ARM's NVIC to RISC-V, except better. You can implement an extremely efficient scheduler that guarantees deadlock-free concurrency: bare-metal, real-time, hardware-accelerated "Fearless Concurrency," on an MCU with no RTOS![1] Its appeal is so great that, despite still being a draft spec, the leading RISC-V MCU designers are adopting it. Espressif's ESP32-S31 has it, for example. The chaotic emergence of this awesome thing is what is condemned as an "indictment."
Speaking of ESP32-S31, it's going to be a monster when silicon becomes available in quantity. This RV Embedded writing mentions MMUs a lot. Guess what? The S31 has an Sv32 MMU. It can run Linux. Not μClinux. Real Linux. It's already been done twice (that I know of) on the Espressif eval boards. People like Armstrong Subero are going to change the world with it.
That's the froth of RISC-V. The ground is shaking, and the peanut gallery of ISA wizards has no power over it. In a few years, after RISC-V has lain waste to our world of proprietary ISAs and Western IP regime rent seeking, "They Should Have Known Better" will look as silly to everyone as it already looks to me.
ESP32-P31s are cheap - samples are cheap ($5-6 for WROOM modules) production prices are going to be lower - and twice the number of pins ESP32s are known for (but say goodbye to castelated modules hand soldering is going to be harder)
A fun fact about ChatGPT and its ilk is the final RL polishing of the responses was outsourced to Nigeria and other places with cheap labor, so the patterns you’re picking up in the article aren’t that the author sounds like ChatGPT, it’s that ChatGPT sounds like the author.
Same reason the southern accent has overlaps with west African dialects.
Just an unlucky spawn point. We need to focus on ourselves. "oh no shipping to some remote island is expensive compared to NYC that has next day free on everything" Well, duh.
It's a distasteful take to be sure. But, what is GP supposed to do?
Frankly I'd rather be told that than the other common but tired SV-resident take of "just hustle, bro, stop sleeping, hustle hustle hustle. Learn to code, take loans from friends and family. Doesn't matter that you're born in a shithole, I was born in a median family myself, we only had one car and we rented our house!!! Just gotta work for it, everybody can achieve it. Those who don't, are clearly not working hard enough."
Naïve take. We live in a global neoliberal economy, our standards of living are the direct result of introducing scarcity and other forms of exploitation elsewhere while keeping domestic populations largely unaware of how unfair their position is. There is no ethical basis to simply "focus on ourselves" here. We must do the exact opposite.
Let’s take the rationalist approach, then: does the author of this blog post seem like someone who could contribute reasonably to humanity’s future? Does it seem like we might be doing ourselves a disservice by ignoring them, and those like them?
“I am, somehow, less interested in the weight and convolutions of Einstein’s brain than in the near certainty that people of equal talent have lived and died in cotton fields and sweatshops.”
― Stephen Jay Gould
Edit: y’all really don’t like being told you should care about other people, huh?
yo this is actually some really fire reading. i had to read it twice then go back and read the original that he's responding to here. i feel full of wonder right now seeing people who are this deep into compsci debating merits in the marketplace of ideas, there's just so much going on globally with computing that i never even get to see. super fascinating to read about the different constraints at play here even the global socioeconomic ones and how they apply to the chip world in general. it sounds like risc-v's real play is democratizing access to the entire embedded stack
The only real point of contention I see between the two is that this piece goes on to talk about how it's a selling point that RISC-V can be used for both low-end 10 cent microcontrollers, and high-end multi-core processors running Linux. Personally I don't see the benefit of this since you're going to have to recompile your software anyway, and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
Dmitry is talking about high-end application processors that you might find in a mid-range or better laptop, smartphone or server. Armstrong Subero seems to think that anything larger than a "dirt cheap microcontroller" is high-end.
People shouldn't take this the wrong way, but the VexRISC-V cores in Baochip are not "high-end". They are basically as low-end as you can get while still meeting the modern definition of "application core". And that doesn't matter, because being high-end application SoC is not Baochip's design criteria. These cores are actually pretty decent for Baochip's criteria.
The VexRISC-V are implementing the exact style of "classic-RISC" microarchitecture that RISC-V is optimised for. It's basically the optimal niche for RISC-V, before any of the problems start showing up.
I don't think I've ever seen anyone express the opinion that RISC-V can't easily cover the "dirt cheap microcontroller" to "low-end application processor" range, even stretching up into "mid-range application processor". Just that it's really fighting an uphill battle if it ever wants to compete with high-end application processors (and that it's going to struggle in the low-range/mid-range application market because of that).
Anyone who spends $200 million to develop a completely new high-end processor microarchitecture every 3 to 5 years is not going to complain about an ARM license too much. You get freedom with $$.
Not as much freedom as they would get with something open like RISC-V, as ARM have strict rules around private ISA extensions (like how Apple doesn't publicly document AMX). But that extra control is generally a good thing for the health of the wider ARM ecosystem.
RiscV is going to win despite its limitations, simply because they can be worked around freely, and the cost per core is zero. Every major company will be making their own flavor, because it’s the only way they can economically own the product of their work. Not many companies can be Qualcomm or Apple, but when a company invests millions in an architecture, they want it to be an asset on -their- balance sheet. It may not be the best starting point, but it’s the only journey that ends in ownership without starting from scratch.
X86 had dominance for decades not because it’s the best architecture, but because it was the best choice. RiscV doesn’t have to be the best architecture to be the best choice for companies to build on.
He talks about them being the "10c/chip" chip.
Then, there is the CH32v303 https://www.wch-ic.com/products/CH32V303.html, which is the lower end of the chips that support minimal floating point and USB host/client. These ones are a bit more pricey, https://www.lcsc.com/product-detail/C5456849.html at $US1.72 each. The extra price is QFP64 (64 pins, quad flat pack) and more features on the chip, USB, CAN, V4F extension giving one instruction multiply and some floating point operations.
Note that the fact that this chip uses an extension, V4F, for floating point (I think?) is part of the argument of Dmitry's piece on the RISC-V. The chip is pretty low price for a fair bit of power.
I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations?
If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanently crippled perf, or find a way around the issues.
--
[0] Making chips is an extremely high tech process with decades of trial and error and proprietary secrets, so this would be the logical explanation to me regardless of architecture. But I'm not hardware guy, so I'd love to hear more about this!
Not quite. RISC-V application class processors are a new development. They are starting from behind but they are improving faster than the competition. The SpacemiT K3 is 4 times faster than the K1 for example. The Alibaba C950 will be about Apple M1 level performance. And even faster designs are already in the works.
RISC-V is not “permenantly crippled”. It will catch up and maybe surpass ARM. It is more an economy of scale issue than anything.
Intel and AMD have proven that if you throw enough money at the problem, you can make fast microarchitectures despite a flawed ISA, and in many ways RISC-V is less flawed than x86. The things we are debating here are more along the lines of minor nitpicks.
The main roadblock to the existence of fast RISC-V cores is the entrenchment of large x86 and arm ecosystems.
I'd disagree with that, their existence and decades of a head start mean they've been much more well invested but that's one of the things we're starting to see change, even if it's because of what would appear to be political motivations. We're starting to see a lot of investment into it in China because it looks like it's a reasonable way for tech sovereignty against the x86 monopoly. They've got licenses to some older (not sure about newer) AMD processor designs, I think around Zen2 architecture, for one of their major manufacturing firms but that won't easily let them move forward since they've got to do a lot of work to keep it up with compatibility and performance for newer ISA additions and such. That's one of the reasons they've been subsiding development of LoongSong64 and RISC-V to the point where for a while the larger LoongSong64 cores were illegal to export to some countries[0].
And then you've got a lot of other companies building faster RISC-V cores, for yes more embedded style designs but not the usual traditional embedded designs either. You've got TensTorrent working on AI work loads with real hardware out there that at least for ML stuff can compete on inference if you can get your software to run on it, and then you've got Bolt doing similar for GPU workloads[1]. While both of those are closer to embedded since you're not going to use them as a desktop, they're still making really fast RISC-V cores that could be theoretically turned into a standard RVA23 core by adding the missing extensions to make it work. That's of course not trivial but the entrenchment of x86 and arm aren't quite as daunting as they might have originally seemed.
It's still not as fast as I'd like, simply because I want to start seeing some RISC-V mini pcs get made that are fine for a daily driver office pc to happen.
[0] https://www.tomshardware.com/news/china-bans-exports-of-its-...
[1] https://bolt.graphics/
And yes, there is a bunch of funding being pumped into it. I do have hope that some kind of RISC-V linux workstation will be viable in the next 5 years, without sacrificing too much performance or my wallet. I just wouldn't expect that to translate into making inroads into existing markets where x86 and arm have moats, like android/apple smartphones and more typical desktop/laptop workloads (even on linux).
I wouldn't count the AI/GPU stuff, those are generally pretty simple RISC pipelines with large vector units. Though TensTorrent do actually have a high-performance out-of-order rva23 core [1] that would be able to compete in this space. They are currently selling it as a "core for agentic workloads"
[1] https://tenstorrent.com/en/ip/risc-v-cpu9719654910d.pdf
Not having decently performing risc-v chips right now doesn't mean anything other than nobody spent enough time and money on accomplishing that.
Because, without neglecting the micro-architecture, we all know how critical the silicon process is for high-end performance.
Riscv took all this information in, and designed a very, very good brick.
how will that pan out over the long term is really unclear and the reality is performance is actually catching up quickly
This has always been true, it is just this is one of those projects that gets some people very emotionally invested so such discussions do not happen in public.
See also Android, rust, webassembly, webgpu and so on.
As much as people complain about warts in other ISAs like x86, their design decisions made sense back when they were made (or at least, no one really knew better)
The benefit is a unified toolchain. Make a chip, get the entire software toolchain for free.
In the past if you made your own chip you had to write your own assembler, compiler, debugger, etc. Many manufacturers forked gcc but of course it's still a lot of work and the license isn't great (for them, not the user).
This universal compiler toolchain is massive benefit for both the chip makers and the end user.
So it is with the family of mutually incomprehensible ISAs called RISC-V.
And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.
I assume this is addressing
> and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
If so, could you point at specific SBCs that beat ARM SBC perf?
And I will note that the other poster didn't say they beat it, just that there are lots of chips being built. I'd imagine that the cores on the tenstorrent cards would blow all the other arm cores out of the water if you could run the benchmarks on them directly, given the much higher core speeds and memory bandwidth etc.
[0] https://youtu.be/vSKA6thLI1U?t=993
Any examples of this?
* Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIMD registers to the destination. There are however some instructions where LMUL=2 only needs to write to one registers, those are narrowing instructions (e.g. 64-bit to 32-bit truncation) and comparisons (which write to a LMUL=1 register with packed bits). When those SIMD instructions have to .vx form, which means one argument comes from a GPR, they now only need to write one SIMD register and need to read two SIMD registers. This matches what regular SIMD instructions need and because the silicon for the execution is much cheaper than register file ports, Ascalon can exexute these instructions in a single operation. So you can compare twice as many SIMD elements against a scalar, then you can against another SIMD register.
* Ventana (now under Qualcomm) talked a tiny bit about their fetch-block-optimizer and something that sounded like a L1i-trace cache. The fetch-block-optimizer would go to certain hot L1i entries and "optimize" them, with agressive instruction fusion including fusion of non-adjacent instructions.
* NextSilicon: Idk any details yet, but they said they handled RVC without increasing latency and that they've found a good solution for implement RVV and especially LMUL, which is a challange in out-of-order designs.
* OpenXiangShan: The fastes open-source CPU, is working on doing 2-ahead instruction fetch (the thing Zen5 added).
Now that being said, Ventana was bought by Qualcomm, we know the RISC-V team is still alive, but who knows if we'll ever see anything from that outside of Qualcomm?
The Tenstorrent Ascalon devboard is way behind schedule and on 12nm TSMC instead of a 4nm node the processor was designed for and is now supposed to clock at 1.38GHz. Though I think the delay has more to do with TT management problems then with the actual design.
While the scalar part of OpenXiangShan looks really good, the RVV imolementation is currently basically unusable. They want to have fix for the problems until the end of the year, but we'll have to see.
Good news! It seems they just opened a new PR for a new RVV implementation: https://github.com/OpenXiangShan/XiangShan/pull/6331
The improvement is entirely "we don't have to pay ARM"
Sure there are. If you want to do weird and wacky stuff, try to do it with an ARM and see how fast you get shut down.
> The improvement is entirely "we don't have to pay ARM"
No, it's "we don't have to beg and grovel, or pay ARM."
Of course, in the more distant past, AMD and Intel sued each other a lot. But there have been a dozen or so x86 market entrants. I think the competition has just been brutal.
So, with either one, you could, of course, do a clean-sheet design and hope you don't get sued.
Since ARM has historically only sold IP, they are incredibly jealous of their monopoly for that ISA. Of course, the flip side of it is that if you have enough money, and you beg and grovel enough, you can probably do what you want with their code.
Except, of course, when you can't. Or rather, maybe you can, but they will try really hard to stop you.
For example, Qualcomm, an architecture licensee who had purchased the rights to basically make whatever the fuck ARM they wanted, purchased a startup named Nuvia that also had an architecture license, and started using Nuvia's designs.
ARM sued, just because. They were shut down in court, but the message is clear. They are very aggressive.
Seriously, who needs that shit? Semiconductor market windows are tight enough as it is, and ARM has always acted like "Nice chip you've got there, buddy; shame if you haven't dotted your i's anc crossed your t's on the licensing."
At least with Intel or AMD, you're probably only looking at patent lawsuits, and you could probably do a decent job on a low end machine with techniques that were known 20 years ago.
You could do the same with ARM, of course, but they will sue you just because, to see if they can make you run out of money.
I don't get how both things can be true. The cost to ship something to Trinidad and Tobago has nothing to do with whether it's ARM or RISC-V; shipping the same weight of either kind of chips should cost exactly the same amount. Yes, maybe the chip cost itself of a particular ARM-based model is $0.15 while the equivalent RISC-V chip costs $0.10, but if the issue (for him and other people who live outside US/Europe) is that shipping costs are orders of magnitude more expensive than the thing being shipped, that chip-cost difference becomes irrelevant.
I think he does make a great point about how fragmentation does give you better optionality: ARM is sort of like cable TV where you have a small number of product categories that each bundle a particular set of features, whereas with RISC-V you design something bespoke that does exactly what you need and nothing more. But again, this isn't going to affect shipping costs.
Aliexpress doesn't do any ID verification hassle. This is all an argument more about distribution and shipping. RISK-V is going to win because getting the parts is insanely cheap and without overhead.
The "fix" is probably Digikey, Mouser, and Segger need to just let buyers check a box where they assume all liability and parts are just thrown in the mail and forgot about - something aliexpress is great at doing.
A quick search for "arm chip" on AliExpress shows lots of results, so I don't think your argument refutes anything I said.
Living in the US and having free overnight delivery is 1st world luxury
STMicroelectronics also launched the STM32C0 series that is still quite cheap @ ~0.35$/piece.
However, the prices on aliexpress all mishmash so giving a correct quote is impossible as the same chip is sold at wildly different prices by different sellers.
This is 100% written by Claude. I've seen this sentence structure hundreds of times per day. That might be your answer.
But it doesn't change the question; I still expect authors to be responsible for the meaning of what they post, regardless of whether they fully wrote it themselves or not. Yes, I know, silly me.
This is a really constipated sentence and there are a dozen better ways to say it. Claude loves this structure though.
Then probably RISC-V being "open" license is the key to its success, even if the architecture itself is weird.
This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86 computers of the era.
However, people were buying x86 computers at a far higher rate, giving Intel (and AMD) the money needed to invest in better chip designs and better fabs. Linux was, at the same time, gaining traction and, around the time the dot-com bubble popped and there were no longer companies with the money needed to get Sun SPARC workstations (or what not) at $50,000 or more a pop to start up a web business, x86 computers running Linux had nearly the same performance at a much lower price. Once the Itanium sank and x86_64 was mainstream, x86_64 was the ISA of choice for performance workstations and servers, and the RISC ISAs that survived were now mainly used in the embedded space. Indeed, ARM was never a high performance RISC processor, and it was the one that took over the embedded space while PA-RISC, Alpha, and SPARC died.
The ISA for what were cheap computers become the highest performance ISA around.
It has been only in the 2020s that RISC processors have gotten x86_64 levels of performance, notably in the the Apple M series of processors. So now ARM, an ISA which was geared for cheap embedded devices, has become a high performance processor, in line with x86.
Right now, RISC-V is mainly being used in cheap embedded components. Considering that x86 and ARM also were made for cheap computing, until becoming the dominant high end processor, history tells us that the cheapest ISA is the one which will become the highest performance one.
RISC-V currently has about the same performance as a high end Raspberry Pi. I predict it will have medium-level PC performance by the end of the 2020s.
In terms of a “theoretically even better ISA”, if anyone has any proposals, I would love to see links to them. In particular, the article “RISC-V: They Should Have Known Better” does not propose an ISA (except mentioning that the author feels AArch64 is much better), so I find its criticisms dubious.
[1] I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers, but 16 registers at least is quite a bit better than the 4-8 registers the 386 had.
Is "registers" still a real thing or its just an illusion at this point? I am pretty sure there are "virtual" registers or micro instructions (something like that, I forgot the terminology)
> From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings
Yet earlier:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
Seems to me that the difference between a 10c chip and a $1 chip are a rounding error when the shipping cost dominates so much?
> I can pick up H417s on the official WCH store on Aliexpress with free shipping and no verification hullabalu.
I think the point is that anyone can make these chips, so there are Chinese sellers who just throw them in a padded envelope and send them out without bothering with all the stuff "serious" vendors do. And because they're cheap enough, if doesn't matter if some get lost in the mail.
If Quintauris successfully makes a RISC-V range for automotive use, there'd probably be margin to clone those and sell at a profit, but skirting automotive certification regulations is a high-risk game that (hopefully!) doesn't have many buyers.
If they make an IoT line, again, there might be margin in it, but you'd be trying to fit in between buyers willing and able to engage with Chinese sellers but for some reason unwilling or unable to engage with existing Chinese sellers of existing IoT RISC-V parts. Quintauris is a very, very long way away from being a "household name" along the lines of STM32 or FTDI.
I don't know why you'd take that as a given when marquee RISC-V microcontrollers are almost universally low-cost, but Arm has pricier marquee parts, thus a bigger opportunity for undercutting the market leader on price with a cloned product.
So per unit shipping collapses with quantity, which is why the part price matters more here, not less. The fixed cost forces you to buy deep, and only the cheap part lets you buy deep. At a dollar a part, 1000 units is a $1060 order nobody here is placing... at ten cents it is $160, and then there are 1000 parts sitting in Trinidad that nobody else has to pay $60 to reach, so you can have enough for a small product run..keep in mind we also currently have US dollar shortage, so you only get allocated a certain amount of US per quarter....
I should also have been explicit that those figures are the Western channels like DigiKey, Mouser, courier from LCSC. WCH officially sells direct on AliExpress with free shipping, which runs on postal consolidation rates that do not price by how remote you are. But that channel is a game of chance. Sometimes things just never come, there is no ARM equivalent either. I cannot buy an STM32 from ST with free shipping to Trinidad, and I cannot trust the aftermarket parts because some of them are fakes, and some vendors do not have this country in their shipping list at all....
The part I care about most is that at ten cents I can hand a student a part they are allowed to destroy. Learning embedded means killing chips, and at a dollar a part a teacher flinches, cause 1 US dollar is about 7 dollars here, and starts supervising instead of letting people find out. And the same goes for me, at ten cents I can experiment and still ship with the part I experimented on....
Ah, I think that explains my confusion (in a different top-level comment[0]).
I read the wording in your article as you getting shipped "a dollar worth of chips" or "a dollar of chips", which to me sounded like you were talking about ordering multiple chips. So I assumed that the per-chip cost for ARM and RISC-V were close enough not to matter too much, and the shipping cost easily dominated.
But now I see it says "one dollar chips" (either I read it wrong initially, or you've updated it since I read it), which makes sense. $1 vs. $0.10 is a big difference at even smallish quantities. (My assumption was that the chip cost difference was more like 1.5x, not 10x.) And while the shipping costs are huge enough to dominate regardless, being able to order 10 chips vs. 100 chips for the same price (and presumably roughly the same shipping cost, even if it is high), is a big deal. The "allowed to destroy" bit is very real.
I thought your argument was about shipping costs, since that's what you focused on so much in the article, but the real issue is still the cost of the chips themselves. The ridiculous shipping cost you have to pay is certainly a factor, but I think a teacher in China would still flinch at giving a student an easily-destroyable $1 part, vs. a $0.10 part, even if their shipping costs are basically nothing.
[0] https://news.ycombinator.com/item?id=49323318
> The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh
It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile delivery costs are fairly low there too.
The typical bay area centric take has the following vibe:
1. I am among the group of most open minded people
2. I admit mistakes, but I don't change my view, that means I may make the same mistakes next time on a different concrete cases
3. Morally I am among the least corrupted
4. I work for the moderately morally questionable firms with nice paychecks, but my moral views are not tainted a bit
5. I never think on the other's perspectives
https://www.astralcodexten.com/p/the-foothills-of-bay-area-h...
My favorite bit, I think (along with the running gag of the constant use cases/connections that somehow pop up for Epstart’s founder):
> “Would you like to hear more about how copying AI tics helps me keep conversations going?”
> “Uh, sure - wait! No!” You break off and turn around as fast as you can.
If the other entries in the series are anywhere near as good, I’ll have some reading to do now.
Bangladesh is a country in Asia...
In my experience, the only demographic who complains about “Asia = east Asia” are people from South Asia, aka Indians/desis
1. "Asia" and "Asian" are different words, which mean different things.
2. There is a dialectal difference specific to "Asian" between England, where Pakistani immigrants are prominent, and the United States, where they aren't.
The term for East Asian was Oriental which is now considered racist/passé for some obscure reason.
I imagine both the majority of shipments from Asia, and the majority of shipments to Asia, fall into this "nonsensical" category.
So don't even try to find how expensive is bring these to Brazil. Even the $5 orders from JLCPCB become infeasible for hobbyists here due to all the roadblocks.
HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with SWE culture in DACH and CEE.
Presumed RISC-V hate is a perfect example of that - the UCs and CSUs have been using RISC-V in their curriculum since the 2010s becuase Patterson is faculty at Cal and most CompArch courses in both systems have been using RISC-V as a result because 61a/b/c are often used as the benchmark curricula wise. An entire generation of Californian computer engineers have been RISC-V fluent as a result.
The hivemind assumption that HN's user base is "venture capital", "tech bro", "founders", and "Silicon Valley" is around 5 years out of date.
Anecdotally, the vast majority of younger (below 30) founders, engineers, VCs, and builders in the Bay have either not heard of HN or quit it within weeks due to toxicity.
I honestly do not get this at all. HN remains very US-centric to me, and especially centric to the mindshare of the Bay Area's IRL conversations, and apart from some takes on tech rights, does not really remind me of my experience in DACH.
>> HN remains very US-centric
Bay Area != US
The Bay Area is its own microcosm of culture and philosophy that diverges significantly from much of the US.
Not making a statement on how prevalent either are on HN, but Bay Area is very much not equivalent to the US.
Extremely. The valley/startup lens is absolutely the dominant one.
The majority of HN's usership, posting, and comment activity occurs during peak EU work hours (3am-9am), stylistic patterns that are common for German-, French, and Polish-native speakers are increasingly prominent (eg. periods and spaces instead of commas in numbers, spacing between quotation marks and words, failing to use context clues to infer timezone), and the fact that IRL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase.
HN "Who wants to get hired" threads are a good example of that as well.
I'd recommend deep diving in the HN scrape dataset on HuggingFace [0]. The site has diverged heavily compared to 2018 or 2012.
[0] - https://huggingface.co/datasets/open-index/hacker-news
For starters, most Bay Area residents are not active on HN on a sunny Sunday afternoon during peak brunch time, a Giants v Rockies game, a social race in the Marina, during the weekend right before college move-in begins for a number of UCs, and the first weekend after the K-12 school year started.
Secondly, the technical conversations on this HN are somewhat divorced from those which are common now. Firstly, no one cares about system cards or micro-level model changes and performance anymore - the name of the game now is eval, harness development, RL/reward engineering, and model-agnostic development.
Thirdly, the vibe change around layoffs the job market is completely different. While there have been plenty of layoffs (and friends and acquaintances of mine have been impacted), most have been able to land jobs within weeks with a similar base/bonus/equity structure.
Furthermore, the Ivy-versus-nonIvy division and rhetoric is nonexistent in the Bay. Everyone here knows a UCLA grad has the exact same opportunties right out of college as a Stanford grad. Most high value careers like startups, PE/VC, big tech, etc recruit from a mix of 20-30 public and private schools that I have listed multiple times on here. And to add to that - "MBAs" as a moniker is nonexistent as most of us who are in decisonmaking roles here in VC, Corporate leadership, and mid-level management are engineers who never did MBAs or any kind of grad school (except our Chinese/Indian peers because of the F1 OPT).
Additonally, most people are levelheaded about AI - they don't deride it as useless but they also don't think it's going to destroy all jobs. On HN you get very black-and-white and highly polarized thinking that AI is only going to lead to X or Y.
And finally, I notice a degree of European anti-Americanism and American anti-Europeanism that is nonexistent in the real world. I have co-hosted events with EU consulates, helped direct European startups to get American funding, and vice versa, and had pretty personal and unfiltered conversations over drinks with pretty high level Europeans and Americans, and the kind of acrimony you see on here is nonexistent IRL.
Not a single mention of pickleball, hyrox, Kdramas, Yemeni coffee, women's basketball, and other stuff currently in the zeitgeist in the Bay is very telling.
Luma was always a public events app optimized for discovery. Partiful on the other hand was meant to be a a replacement for FB private events when hosting a house party or private gathering. Basically, Luma was always designed for M-F and Partiful was always meant for Sat/Sun.
" RL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase. " Any proof?
So what does "the majority" mean? 51%? Because that's just saying those 51% occur during EU/UK afternoons and east cost mornings.
I like to encounter discussions about German digital health system or the German start up system or neo2. I've never seen them so I doubt it.
Also almost no debates about Polish stuff (Hello neigbours!)
fwiw, my experience is similar. hn has not been about startups, vc funding, or anything in that space for quite a while.
to paraphrase a classic, this place is like a memory of the forum we used to love, and the memory is fading.
Well, this place (wherever you are) is like a memory of the world we used to love, and the memory is fading... Definitely true too.
You can't expect a place tightly connected to a changing world to stay the same.
For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM is better because it has a "store multiple registers" instruction. It wouldn't help because storing multiple registers still requires multiple bus cycles, and microcontroller probably has a 32-bit bus and no cache, so saving N registers requires N memory cycles - no matter, is it done with a single instruction (ARM), or with multiple (RISC-V). And implementing this ARM instruction makes the core more complicated with little benefit.
As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment.
The real weak points of RISC-V are:
- no trap on integer overflow and invalid FP results . Overflows cause vulnerabilities
- no optimizations for fast context switch, which is required for dumping legacy unsafe monolithic kernels, especially in age of AI actively searching for vulns
- weird vector extensions
His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?
The problem is that RISC-V is never going to win at the high end. RISC-V will never have as much money driving it forward as x86 and ARM. As such, the blocks and integration will always lag.
The portion of the market which RISC-V could dominate is the low-end (you know ... the same way ARM climbed up the ladder?) and nobody in charge of RISC-V cares because you have to actually ... SHIP FREAKIN' CHIPS ... and that's, you know, so icky.
And this is the disconnect. Low-end embedded has a bunch of needs and the RISC-V architecture completely whiffs on many of them and has active misfeatures on others while having very little that is actively good in that space.
And many of us are angry about this. It didn't have to be this way.
Maybe I'm missing something important so far...
It definitely could have gone with a less abrasive tone (as entertaining as it is), so it's no wonder it's getting some pushback.
Before this, the author has never recommended others stay away from RISC-V, just stated their own distaste for it and a personal preference to use any other ISA if given a choice.
I just think that if you were designing something from scratch, you could actually learn from past lessons, rather than publishing a document saying you learned, and then demonstrating conclusively that you didn’t.
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
then follows with:
> the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings.
When shipping is so expensive, doesn't the difference between $1 and $.10 unit cost become less relevant?
Though it feels a bit strange that "I have exceeded the allowed number of requests. (500 times)" when I first clicked the article and I'm pretty sure I don't share the ip of my self-hosted VPN with anyone.
I mean that is not even 10 page view per second. We are not living in 2006. Actually even in 2006 Apache with static page would have been able to handle that on a small VPS. And that is excluding CDN.
This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.
And the approach you mentioned here:
> a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA
I think this is basically WebAssembly and PTX, and one may argue, Java bytecode. Yet look at how much efforts and time it took for WASM runtimes and JVMs to actually produce performant machine code (the "last bit per ISA" you mentioned) for just a couple of architectures! (e.g. X86 and ARM). And I wouldn't surprised if NVIDIA pour even more money on building optimization pipeline from PTX to each of their different uArchs.
I bet it would be pretty easy for a user to interoperate between 67 different drafts of the HTTP spec once they were all written, validated, and library implementations coded. But what would that Cambrian explosion of API revs actually get you?
And while things has died down a lot in the past few years, there is a reason why I wrote the line.
"You do not criticise The Rusted Holy Grail and the Riscy Silver Bullet."
>This is almost satirical.
That's all that needs to be said.
It's like comparing Unity and Godot. Unity is better in every single way but one, you have to license it from a very poorly ran company.
You don't "own" your games, they ship with black box spyware. The pricing for using it can change from day to day.
I swear the Unity C level employs a Magic 8 Ball and consults it for key management decisions.
If you need to edit the Unity Engine source code your looking at a secret additional licensing fee which is certainly unaffordable for hobbyist and most indies.
Vs Godot which is completely free under the MIT license.
Everything about the above can be said for ARM as well.
RISC-V is free for everyone to play with. If you think it sucks you can always fork it and jerryrig it to work on existing hardware.
If you have money you can even get custom hardware for your forked RISC-V.
I very much enjoyed reading this article, I'm optimistic in seeing what OPs students come up with. This is life changing technology that's essentially available to all.
The 386 and 486 patent should have expired more than 20 years ago. No one tried to open source it. https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/0... There were many companies that had clones in the early 90s, and I wonder whether any of them still have the rights to manufacture them.
" That is a better reason than elegance. and I want to tell Mr Grinberg, that the word priviledge he tosses around in his article also extends beyond the ISA depending on where you are in the world."
Grinberg is an emigre from Ukraine, which isn't the most privileged place in the world. In fact his research articles go deeper than the average software developer in Silicon Valley.
Edit: It also appears Nvidia might also have an x86 license: https://www.nvidia.com/en-us/drivers/uli-m6117c/
Also, https://www.tomshardware.com/pc-components/cpus/intel-licens... (Caveat: The startup is acquainted with the Intel CEO, so it's rare for them to grant the x86 license to non-buddies.)
"Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere."
What's interesting is that a startup with limited funds would most likely seek a 32-bit x86 license if a) they don't need more than 4GB of RAM, and b), if they don't want to pay AMD for the 64 bit license add-on. :)
OpenFirmware came out of OpenSPARC and is also used by POWER too. Parts of it are used in ARM and RISC-V today (mostly DeviceTree, though arguably quite badly).
Nobody actually wants to make good cores for cheap. Nobody wants to make compatible systems unless forced to. That's why ARM and RISC-V are fragmented messes.
I would personally love to see more Power Systems based projects. Everything is out there, just someone has to want to do something with it.
Fedora Linux even fully supports POWER8+ little-endian systems, and Fedora KDE offers a live ISO you can install on something like a Talos Workstation.
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-Sep...
Cyrix famously had to skirt IP laws by using TI and IBM foundries because those two companies had full Intel 3rd party licenses. Cyrix was sued and paid big bucks settlement just to be able to use Intels patent 338 (long expired). Later cross licensing had little to do with Cyrix, and more with National owning crapload of patents they could use to retaliate against Intel - that 1998 deal https://www.intel.com/pressroom/archive/releases/1998/CN0203... resulted in full cross licensing allowing National build straight 1:1 copies of Intel chips if they desired.
When VIA bought Cyrix from National they didnt inherit ANY of those licenses. VIA was sued just as original Cyrix and National did, and once again had to pay big bucks to settle despite just aquiring Centaur with a bunch of patents and Intel license https://www.pinsentmasons.com/out-law/news/intel-and-via-set...
To do that they, at least, should still exist. For most of them this is not the case.
So, these freight forwarders rent a warehouse in the US, an LLC in the US for paying rent, and give away the address of the warehouse to their customers locally. Customers use the address when shopping online and their packages are dropped off at the warehouse. Then they employ people in the US to collect customer packages in the US into large bags, which are then shipped to the destination country via DHL.
DHL does charge the exorbitant shipping to third world country fees of 35 to 60 to 200 dollars that people here complain about. These fees are the base price for shipping, no matter how small or light the package is.
Then, to recover the fees, packages are handed over to customers at a minimum of 2.50 dollars per pound, per package.
For the business to work, income from these packages has to exceed the shipping cost. In Panama, you can probably fit 100 average packages into a 25 pound bag. That bag costs like 75 dollars to ship from the US to Panama. Then you make 250 dollars when people collect the packages. Local customers trade speed for cost, trading the 35 dollar base shipping price for 2.50 dollars and an extra week of lead time to wait for collection to complete in the US. They also don't have to go to the airport to pick up their packages since the business is ideally close to their house.
Businesses like Temu ship directly from china via companies such as PRS logistics and J&T express so their shipping costs to third world countries are lower and can thus bypass freight forwarders entirely so freight forwarders only remain for items sold within the US, where shipping to third world countries has a base price of at least 35 dollars, and whenever shipping to your country costs that much as a base price, even if it ships from China, or when a business only offers shipping to or within the US.
Sometimes, temu is more expensive than a Freight forwarder, but the user is freed from having to handle any logistics like using a particular address and choosing and registering with a package locker and travelling to pick up packages there and the shipping price remains under 10 dollars. However you still have to use a Freight forwarder for items over 120 dollars such as laptops and some car parts because temu doesn't carry those. Freight forwarding is also done in the exact way described above in China instead of the US because websites like taobao rarely offer overseas shipping. Again employing people in china and renting warehouses near airports there. Freight forwarders also offer marine freight instead of the default air freight.
Of course, renting a warehouse and employing people in the US is expensive by local standards. Worker pay alone is around 1600 dollars vs 600 locally. So, there are only a few freight forwarders which often offer b2b, and then package lockers use their sevices. To the end customer there is no distinction between a package locker and freight forwarder. Some freight forwarders also offer B2C package locker services, others are B2B only.
For example nelcon cargo, Uno express, airbox, mail boxes etc are vertically integrated because they are both B2B and B2C, cft cargo is B2B only. most package lockers do not do freight forwarding themselves and use a B2B service for freight forwarding, the package locker only offers proximity and thus convenience to neighborhood customers. Air freight via Miami international airport is the default, and most freight forwarder warehouses are located near this airport. In China, the bottleneck is not price, but speaking Chinese, so it is often run by locals of Chinese descent and is more niche than shipping from the US. This also means that taobao has a lower shipping volume and thus a smaller local market.
Buyee and Zen market, so called proxy services, are very similar to freight forwarders but the service is allowing foreigners overseas to purchase in Japan because most japanese companies do not offer overseas shipping. And there are a few freight forwarders in china as well.
You have exceeded the allowed number of requests. Your Requests: 500. Request Limit: 500 per minute. Tip: Please wait 60 seconds before trying again.
A 3rd World Embedded Engineer Learns About Caching Generated HTML The Hard Way.
https://archive.md/9FaRC
https://news.ycombinator.com/item?id=48143997
https://rvembedded.com/products/project-lab/
Definitely interested!
Your Requests: 500 Request Limit: 500 per minute
Your Requests: 500 Request Limit: 500 per minute
with no vpn
> Simply put, the things a high-end CPU needs are diametrically opposed to the things a small cost-saving microcontroller core needs.
> The conclusion he draws is that no single ISA can serve both ends, and that RISC-V fans are fooling themselves, in theory the premise is true. The conclusion does not follow, and I can show you why from three parts sitting on my desk as we speak.
> CH32V003. This is the cheap "RV32EC" with sixteen registers, no multiplier, no divider, machine mode only,
> CH32H417. A dual core MCU that is unmatched in performance to price point and is at the higher end of the MCU line
> Baochip. A VexRISC-V with an MMU built around a stack thats open from silicon to os Baochip-1x: A Mostly-Open, 22nm SoC for High Assurance Applications
Uh, which one of these is a datacenter server cpu? Or a workstation cpu? Or at least a developer laptop cpu? How about a Raspberry Pi 4 level SBC (supporting latest ubuntu and fedora releases, driving a display that runs a browser and plays video ...)
There's a lot of angry indignation but it seems obvious that Dmitry is quite right about this.
But I found this is where this blog post starts making a lot of sense:
> Has anyone tried adding an MMU to a Cortex-M? The physical tradeoffs are real, the difference is that with RISC-V, the ISA owner does not decide for you where that boundary must be drawn. If you want virtual memory on ARM you license a Cortex-A instead, which is a different core family, a different profile, a different negotiation, and a different royalty.
> Compare what happened with Baochip. The RISC-V privileged specification defines supervisor mode and Sv32 paging as optional things an implementation may provide. VexRISC-V is an open core, somebody added an MMU to it. bunnie built a chip around it and runs a microkernel with real process isolation on it
Yeah, that is a good point. We're still in the low-end specialty realm, but that is real interesting advantage for RISC-V, a good reason for it to exist.
As for shipping to Trinidad and Tobago ... this post is trying too hard to turn this into moral issue, but it seems a bit random (OrangePi cost $30 and shipped free? you can also get arm-based and stuff from the same places), and the vast majority of people don't live on semi-remote islands, it doesn't make sense to consider this kind of accessibility above all else, and it's strange to blame Dmitry for not thinking of you here.
Does anyone have an archive?
I read the "They Should Have Known Better" article and forgot it. I've seen this before. I know it's hot air and does not matter, and I can't afford to worry about things that don't matter.
When I say I've seen this before, I'm talking about ancient history: controversies so old and so laughable that they've been forgotten. When, for example, AMD handed the world AMD64/X86_64, the same things were said: fragmentation, legacy+flawed ISA, etc. That has not aged well, and "They Should Have Known Better" won't either.
The "fragmentation" argument has no merit. The jumble of extension names and profiles in RISC-V are, in fact, direct evidence that RISC-V is succeeding: it's the RISC-V ecosystem aggressively, collaboratively and successfully tackling pain points and solving them. This is what RISC-V is supposed to be doing, and it's doing it, and empires are being built on it.
Take this part: "The existence of CLIC and various proprietary 'fast IRQ' / auto-stacking extensions is an additional indictment."
CLIC is miraculous. It's an advanced embedded interrupt controller, and it's wonderful: it brings the equivalent of ARM's NVIC to RISC-V, except better. You can implement an extremely efficient scheduler that guarantees deadlock-free concurrency: bare-metal, real-time, hardware-accelerated "Fearless Concurrency," on an MCU with no RTOS![1] Its appeal is so great that, despite still being a draft spec, the leading RISC-V MCU designers are adopting it. Espressif's ESP32-S31 has it, for example. The chaotic emergence of this awesome thing is what is condemned as an "indictment."
Speaking of ESP32-S31, it's going to be a monster when silicon becomes available in quantity. This RV Embedded writing mentions MMUs a lot. Guess what? The S31 has an Sv32 MMU. It can run Linux. Not μClinux. Real Linux. It's already been done twice (that I know of) on the Espressif eval boards. People like Armstrong Subero are going to change the world with it.
That's the froth of RISC-V. The ground is shaking, and the peanut gallery of ISA wizards has no power over it. In a few years, after RISC-V has lain waste to our world of proprietary ISAs and Western IP regime rent seeking, "They Should Have Known Better" will look as silly to everyone as it already looks to me.
[1] https://rtic.rs/2/book/en/
Some serious stuff he builds on top of those chips.
Same reason the southern accent has overlaps with west African dialects.
Is that really your take?
Frankly I'd rather be told that than the other common but tired SV-resident take of "just hustle, bro, stop sleeping, hustle hustle hustle. Learn to code, take loans from friends and family. Doesn't matter that you're born in a shithole, I was born in a median family myself, we only had one car and we rented our house!!! Just gotta work for it, everybody can achieve it. Those who don't, are clearly not working hard enough."
Don't be a smug asshole? Oh, sorry, that's for someone else.
“I am, somehow, less interested in the weight and convolutions of Einstein’s brain than in the near certainty that people of equal talent have lived and died in cotton fields and sweatshops.”
― Stephen Jay Gould
Edit: y’all really don’t like being told you should care about other people, huh?